E-71388

Area of expertise: Analog Layout
Core Technologies: Automotive
Experience: 9 years
Time On Site: 0% 
    
 	
  • Analog IC Layout Engineer.
    • 
 	
  • Custom Analog IC layout design and verification
    • 
 	
  • Cadence Virtuoso IC6.1.8, Assura, Calibre, PVS, Voltus, Innovus
    • 
 	
  • IP and chip level IC layout, tech. 22nm - 0.5um
    • 
 	
  • Module and chip level layout, power management for mobile devices, RF transceiver, automotive applications
    • 
 	
  • Technologies: TSMC - 22nm, 40nm, 110nm, 130nm, 180nm; GF - 55nm; GF - 60nm ; VIS - 500nm SOI
    •

Share this profile