Senior Verification Engineer 
Responsibilities 
Develop and maintain UVM‑based verification environments for memory subsystems and related IP.
Build and debug co‑verification environments integrating production‑level firmware with hardware simulation.
Integrate, bring up, and debug Memory VIP, transactors, monitors, and checkers.
Drive functional and code coverage closure and manage regression suites.
Apply strong Object‑Oriented Programming fundamentals in verification architecture.
Use SystemVerilog, UVM, and C/C++ at an advanced level.
Perform IP and subsystem‑level verification using industry‑standard simulators (e.g., VCS).
Architect and execute firmware/hardware co‑verification strategies.
Use Python, shell scripting, Git, and/or Perforce for automation and workflow management.
 Highly Desirable Experience  
Verification experience with DDR / JEDEC‑standard IP, DDR PHY, or memory controllers.
Experience with assertions (SVA/OVL), SystemC, and Zebu emulation.
End‑to‑end verification exposure - from front‑end development through lab bring‑up.
Ability to technically mentor junior engineers and contribute to team capability building.