RTL Design Engineer

RTL design and integration of memory subsystem components such as 
memory controllers
RAM
Cache
Buses
PHY
 Develop logic that efficiently moves data between the CPU, main memory, and storage.
Deliver designs up to physical‑design‑ready (synthesis) level.
Physical design is handled by a separate team, but strong understanding of PD constraints is required.

DDR/LPDDR Subsystem Development
Contribute to the definition, design, and integration of DDR/LPDDR memory subsystems used across all product lines.
Ensure subsystem performance, reliability, and compliance with internal architectural requirements.

CDC/RDC
Deep understanding of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC).
He stressed the importance of CDC/RDC expertise -not just tool usage, but deep understanding as this is critical for product reliability.

DFX (Design for Excellence)
Apply DFX principles to ensure designs are:
  
Reliable
Manufacturable
Cost‑efficient
High‑performance
Suitable for long‑term product lifecycle