Highly experienced integrated circuit design engineer, most recently at Senior Principal level in CMOS image sensors, pioneering the development of automotive, stacked pixel arrays.
 	
Extensive expertise in integrated circuit design and silicon validation over 35 years.
 	
Creator of circuit and memory IP, including compliers, optimized for area and power, verified to specification.
 	
Provider of block views to allow seamless integration in SoCs.
 	
High-speed clock tree design. Layout of pitched cells, analogue blocks and chip top level.
 	
Skilled in documentation and ASIL traceability. Named on eight US patents.
 	
Repeatedly adapted to new methods, tools and technologies, often self-directed.