Verification Engineer
Verification Engineer
The Person:
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An experienced lead verification engineer who is a confident, motivated self-starter capable of independently driving complex work packages
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Brings 10–20 years of industry experience in ASIC/FPGA hardware development
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A clear and articulate communicator who can collaborate effectively across cross-functional teams, time zones, and global locations
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Shows unwavering commitment to helping the team achieve high-quality results and meet development milestones
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Driven to learn, grow, and perform at their highest technical capability
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Equally effective working independently or within a collaborative team environment
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Able to quickly learn new concepts and independently acquire the skills needed for the role
Key Responsibilities:
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Provide technical leadership, guiding projects from initial requirements through final design verification
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Collaborate with systems and hardware engineers to define high-level testbench architectures
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Evaluate, adopt, and integrate new Adaptive SoC toolflows and methodologies into verification environments
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Develop, modify, and maintain random and directed tests and associated libraries in SystemVerilog/UVM
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Write, implement, and review detailed verification test plans
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Participate in and conduct code reviews
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Triage, analyse, and debug regression failures
Preferred Experience:
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Strong proficiency in advanced verification methodologies, including UVM, class-based testbenches, VIP integration, test plan creation, constrained-random testing, and coverage-driven sign-off
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Experience with high-speed connectivity protocols (e.g., 100Gb Ethernet, PCIe Gen5/Gen6, AMBA/AXI)
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Proficient in Python with solid understanding of build systems, regression frameworks, and CI/CD infrastructure
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Experienced with Git-based CI/CD workflows
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Skilled in scripting languages such as TCL, Perl, and shell
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Familiar with verification challenges specific to Adaptive SoCs
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Understanding of verification flows for complex embedded processor architectures (ARM, RISC-V, CPU)
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Knowledge of software flows in advanced SoCs, including embedded processor co-simulation and debugging
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Hands-on experience with adaptive SoC EDA tools (e.g., Vivado/Vitis)
Academic Credentials:
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Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related discipline