Functional verification (unit, IP, and subsystem level)
 	
RTL design, debugging, and integration
 	
Testbench architecture and coverage-driven verification
 	

 	
Performance analysis and monitoring
 	
Mixed-signal design and characterization (analog + digital)
 	

 	
Languages & Methodologies:
 	
SystemVerilog, UVM, Verilog, VHDL
 	

 	
Verification & Design Tools:
 	
QuestaSim, VCS, NCSIM, Design Compiler, Vivado, SpyGlass, IMC, Verdi/DVE
 	

 	
Scripting & Automation:
 	
Python, Perl, Bash/Tcl
 	

 	
Bus Protocols:
 	
AMBA (AXI, AHB, APB), proprietary ready/valid interfaces
 	

 	
Version Control:
 	
Git, SVN
 	

 	
Domains & Standards:
 	
SoC/IP verification, Network-on-Chip (NoC), RDMA, DO-254, ISO 26262