{"ID":20216,"post_author":"132","post_date":"2025-07-23 09:54:37","post_date_gmt":"2025-07-23 08:54:37","post_content":"

Analog & Mixed Signal Verification Engineer<\/li>\r\n \t
-Professional skills: Mixed-signal verification, Analog\/digital modeling, embedded system design<\/li>\r\n \t
-Programming languages: C\/C++, Java, Matlab<\/li>\r\n \t
-Scripting languages: Python, Perl, Tcl, Bash, Skill<\/li>\r\n \t
-Languages: VHDL, Verilog, SystemVerilog, Verilog-a, VerilogAMS<\/li>\r\n \t
-Methodologies: UVM<\/li>\r\n \t
-Tools: Cadence verification toolchain<\/li>\r\n \t
-Version control tools: SOS, SVN, GitHub, Design Sync<\/li>\r\n \t
-Understanding and simulation of complex RF IPs<\/li>\r\n \t
-Hierarchical model development and simple MVSS(WREAL, RNM UDT)<\/li>\r\n \t
-Development of config files(Hierarchy editor)<\/li>\r\n \t
-AMS IP and simplified top level simulations running<\/li>\r\n<\/ul>","post_title":"E-67187","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-67187","to_ping":"","pinged":"","post_modified":"2025-07-23 11:16:07","post_modified_gmt":"2025-07-23 10:16:07","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-67187\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"desired_position":"Contract","best_fit":"Analog Mixed Signal Verification","experience":"8","entity_type":"Individual","on_site":"0","technologies":"Automotive","contact":"Annette Burke","level":"Senior Engineer","_edit_lock":"1753265779:129","_edit_last":"129"}}

NO

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E-67187 | Chipright Chipright

E-67187

Area of expertise: Analog Mixed Signal Verification

Core Technologies: Automotive

Experience: 8 years

Time On Site: 0%


 	Analog & Mixed Signal Verification Engineer
 	-Professional skills: Mixed-signal verification, Analog/digital modeling, embedded system design
 	-Programming languages: C/C++, Java, Matlab
 	-Scripting languages: Python, Perl, Tcl, Bash, Skill
 	-Languages: VHDL, Verilog, SystemVerilog, Verilog-a, VerilogAMS
 	-Methodologies: UVM
 	-Tools: Cadence verification toolchain
 	-Version control tools: SOS, SVN, GitHub, Design Sync
 	-Understanding and simulation of complex RF IPs
 	-Hierarchical model development and simple MVSS(WREAL, RNM UDT)
 	-Development of config files(Hierarchy editor)
 	-AMS IP and simplified top level simulations running

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-67187

Area of expertise: Analog Mixed Signal Verification

Core Technologies: Automotive

Experience: 8 years

Time On Site: 0%


 	Analog & Mixed Signal Verification Engineer
 	-Professional skills: Mixed-signal verification, Analog/digital modeling, embedded system design
 	-Programming languages: C/C++, Java, Matlab
 	-Scripting languages: Python, Perl, Tcl, Bash, Skill
 	-Languages: VHDL, Verilog, SystemVerilog, Verilog-a, VerilogAMS
 	-Methodologies: UVM
 	-Tools: Cadence verification toolchain
 	-Version control tools: SOS, SVN, GitHub, Design Sync
 	-Understanding and simulation of complex RF IPs
 	-Hierarchical model development and simple MVSS(WREAL, RNM UDT)
 	-Development of config files(Hierarchy editor)
 	-AMS IP and simplified top level simulations running

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