-Programming Skills: System Verilog, Verilog, UVM, Perl, Python, C, C++
ASIC verify Flow: VCS, DVE, Questa Sim, Functional Coverage, Code Coverage, Constraints,
Randomization, SVA, VIP Flow, TC Dev, Debug Skills, Reusability
Verification CTRL Tools: GIT, SVN, Perforce
 	
 -Protocol known: CXL 2.0, PCIe 3.0/4.0, CAN(FD+FT), Intel UPI, MHL, APB/AHB
 	
 -Experienced ASIC/SOC/IP Verification using System Verilog and UVM
 	
 -Experience working on Protocols: PCIe, CXL, CAN, Intel UPI, MHL and AMBA Protocols
 	
 -Hands on experience in Verification using System Verilog and UVM methodology
 	
 -Experience in Building Verification Environment, Test Plan and Test Case Generation, Verification using SV
and UVM
 	
 -Developed Verification Plans, implemented Test Scenarios, SV Assertions, Coverage, Test Env and
Verification IP
 	
 -Experience in Scripting language: Python, Perl
 	
 -Experience in Programming Language: C and C++
 	
 -Experience working on Version Control Tools: GIT, SVN and Perforce