-Design Verification of Ethernet Switches Chip Design, using UVM TB, SystemVerilog and scripts (Perl, Python).
 	
- FC level and UNIT level
 	
- Work with direct and random tests for functional verification of the DUT
 	
- Verify design using SVA language construct
 	
- Implement UVM agents for stub behaviour accordingly to the required design documentation
 	
- Write coverage to determine the verification depth
 	
- Owner and developer at Unit level TB for Ethernet ANP unit inside the Physical Layer
 	
- Contributor to create and implement workflow template approach for documenting and implementing the verification process at the Full-Chip level team
 	
- Train and guide new engineers in learning and understand the verification processes
 	
- Tools: Verdi, Simvision, Unix, Confluence, Jira, Cider, IMC