E-70968

Area of expertise: ASIC Verification
Core Technologies: Telecommunications
Experience: 7 years
Time On Site: 10%
  • -ASIC Design Verification Engineer with several years of experience
  • -Excellent knowledge of System Verilog/UVM and Specman e language/eRM
  • -Excellent knowledge of developing module verification concepts and reusable verification IPs and environments
  • -Programming Languages: SystemVerilog(UVM), Specman(eRM) Verilog, VHDL C, Python (basic)
  • -Protocols: HDBaseT, I2C, UART, AHB, APB, AXI
  • -Tools: SimVision, VManager DVT, Visual Studio Verdi, NCSim
  • -Version Control: SVN, perf, SOS, GIT