Principal Analog Layout Engineer
Salary: Very Attractive Rate
Location:
Contract Lead
Principal Analog Layout Engineer
- Minimum 5 years experience but ideally >8+ years Experience
- experience in 65nm and below (ideally 22nm and below)
- understanding of layout for critical timing (PLL, DLL, clock distribution)
- understanding of matching techniques for timing circuits and current cells
- chip finishing experience a bonus
- experience of Cadence PVS/QRC/Pegasus
Contact Us
+353 91 444 168
info@chipright.com
Unit 8B, Galway Technology Centre, Galway, Ireland