Digital Physical Design Engineers
Chipright is seeking an experienced Digital Physical Design Engineer to support the implementation and sign-off of a complex digital design using advanced 7nm FinFET technology.
The successful candidate will be responsible for key aspects of the physical design flow, from floorplanning and synthesis through timing closure, physical verification and final sign-off. The role requires strong technical expertise in digital implementation, low-power design, timing analysis and physical design verification, with hands-on experience using Cadence digital implementation and sign-off tools.
Key Responsibilities 
Perform floorplanning and physical design implementation for a complex digital design.
Generate, review, debug and maintain design constraints and Unified Power Format (UPF) files.
Execute logic synthesis and support optimisation of the design for power, performance and area (PPA).
Perform Static Timing Analysis (STA) sign-off and drive timing closure to meet design performance targets.
Analyse and debug Clock Tree Synthesis (CTS) issues to achieve clocking and timing requirements.
Perform Logic Equivalence Checking (LEC), including Conformal Low Power and logical equivalence checks.
Support physical verification activities, including Design Rule Checking (DRC), Layout Versus Schematic (LVS) and Antenna (ANT) checks.
Conduct IR drop analysis and support power integrity closure.
Identify, investigate and resolve physical design issues throughout the implementation and sign-off process.
Collaborate with RTL design, verification, methodology and other engineering teams to resolve design issues and achieve project milestones.
Ensure the design meets the required area, timing, power and physical verification targets.
 Technical Requirements
The design will be implemented using the following technology and specifications:  
Process technology: 7nm FinFET
Metal stack: 1p13m_1x1xa1ya5y2yy2z
Threshold voltages: SVT, LVT and ULVT
Target design area: 40 mm²
Target standard-cell utilisation: 65%
CPU clock frequency: 3.0 GHz (typical)
Primary clock frequency: 800 MHz
AXI bus clock frequency: 800 MHz
 EDA Tool Experience
Hands-on experience with Cadence implementation and sign-off tools is expected, preferably with the 26.x tool releases:  
Genus – Logic synthesis
Innovus – Digital physical implementation
Pegasus – Physical verification
Quantus – Parasitic extraction
Tempus – Static timing analysis and timing sign-off
Voltus – Power integrity and IR drop analysis
 Candidate Profile
The ideal candidate will have:  
Proven experience in digital physical design, preferably on advanced FinFET process nodes.
Strong understanding of the end-to-end physical design flow, from floorplanning through sign-off.
Practical experience in timing closure, CTS debugging, parasitic extraction and physical verification.
Experience with UPF, low-power implementation and Conformal equivalence checking.
A strong understanding of design constraints, clocking architecture and power integrity.
The ability to debug complex implementation issues and work effectively with cross-functional engineering teams.
A methodical approach to problem-solving, with a focus on design quality, performance and delivery against project milestones.
 Project Environment
This role offers the opportunity to contribute to a complex digital implementation project using advanced 7nm FinFET technology, with demanding CPU performance targets and a comprehensive physical design and sign-off flow.
Candidates should be comfortable working across multiple stages of implementation and collaborating with design teams to achieve successful timing, power, area and physical verification closure.