DFT Enginner

Preferred Skills & Qualifications
Strong fundamental knowledge of DFT/DFD techniques for high performance processors.

 	
Understanding of core-based test methodology and scan isolation.
 	
Knowledge in fault modelling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
 	
Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
 	
Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Tessent tools.
 	
Synopsys DFTC scan insertion.
 	
Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.
 	
Working knowledge in one or more of the following; C, C++, TCL or Perl.
 	
Experience with industry simulation tools such as VCS, Modelsim, or others.
 	
Direct experience in silicon bring-up, debug, and validation of DFT features on ATE. 
 	
Detail oriented with strong organizational, problem solving and communication skills.
 	
Experience in design and verification of the above; layout, SPICE simulation, etc.
 	
Experience with formal verification tools such Conformal LEC, Formality, etc.
 	
Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.
 	
Experience with other industry tools such as Vera, Spyglass, 0-in, Conformal Low Power, Jasper, RedHawk, PrimePower.