Design Engineering Architect 
Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe.
Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power consumption, and compatibility with industry standards.
Hands-on leadership of RTL development from micro-architecture definition to IP sign-off for general release.
Contribute to planning of activities and milestones for the digital development teams.
Leadership of cross-functional technical meetings with Analog & Software counterparts.
Support customer pre-sales and post-sales meetings.
Develop, maintain and improve upon processes and procedures for efficient product execution, IP quality and industry best practices.
Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
Job Qualifications:
Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline.
15-20 years’ experience in microelectronics industry.
Expert in Verilog/SystemVerilog RTL design essential.
Expert in front-end design tools covering LINT, synthesis, CDC/RDC analysis essential.
Experience of SoC architecture and development essential.
Experience of technical team leadership essential.
Excellent oral and written English essential.
Self-motivated with excellent planning, interpersonal and with the ability to communicate complex concepts clearly and thoroughly. Additional
Skills/Preferences:
Experience of Metric Driven Verification (MDV) and UVM desired.
Experience of industry standard protocols such as AXI, CHI-C2C & CXS.B preferred.
Experience of quality processes, such as ISO-9001 & ISO-26262 preferred.