AMS Verifier

Salary: Very attractive rate
Location: N/A
Contract Lead
Analogue Mixed Signal Verification Engineer
  • Perform verification simulations and generate design documents to capture key results and performance at block level, sub-system and system level for peer review and future reference for active ASIC development projects.
  • Design test benches in both Virtuoso Analog Design Environment with supporting Verilog A as required.
  • Generate reports and design documents for all key blocks.
  • Record and present circuit schematics, simulation test benches, test configuration and simulation results for review and assessment by the ASIC project team.
  • Ability to spot any performance issues early in the design cycle .
  • Actively  lead and participate in peer design reviews.
  • Contribute to any continuous improvement initiatives.
  • Contribute to ASIC operation manual.
  • A degree (BEng/MEng) in Electronic/Electrical Engineering or equivalent
  •  3-5 years+ in relevant industry in a development role
  • Familiarity with Cadence tool suites  including analog (Virtuoso) but with experience of the digital flow
  • Ability to extract simulation results, clear documentation and presentation skills 
  • Cadence administration knowledge would be desairable



  • AMS Verification