Staff Digital IC Design Engineer with 10 years of progression experience, most recently focused on integrating diverse IP blocks into complex SoCs, developing hardware accelerators for data-intensive applications, and designing lightweight RISC-V processors.


 	
Key Highlights:
 	
-Worked on High-Performance Out-of-Order ARM Custom CPU- REU, including out-of-order microarchitecture and ISA feature implementation
 	
-Worked closely with the architecture team to implement safety-critical design features, including ECC (SECDED), DCLS, and bus monitoring mechanisms
 	
-Languages: SystemVerilog, C, Python, C++
 	
-Tools: Synopsys VCS/Verdi, Cadence Xcelium, Verilator, Cocotb