Senior ASIC Verification Engineer with experience across IP, subsystem, and SoC levels, encompassing full-cycle design verification, integration validation, functional checking, & development of VIPs & BFMs.
 	
Key Responsibilities
 	
Developed expertise in QSB-AHB bus certification within the SSC subsystem for a premium-tier project.
 	
Collaborated with SSC DV/DE and QCT Bus Certification teams to review & refine verification test plans.
 	
Developed and executed certification test suites, performing regression analysis, debugging failures, and implementing fixes to ensure certification readiness.
 	
Led the verification and successful delivery of the Snapdragon Sensor Controller (SSC) subsystem for high-tier and value-tier projects alongside premium-tier commitments, ensuring on-time completion of all DV Q-milestones.
 	
Programming Skills: System Verilog, Perl, C, UVM, VMM EDA Tools Used: Synopsys VCS/Verdi, VC Formal, Cadence SimVision Bus P