ASIC Verification Engineer with expertise in both IP and system level verification,specializing in SystemVerilog and UVM.
 	
A customer-oriented leader with strong experience in functional verification and metric-driven processes, successfully driving closure on multiple IPs features from test-plan development to testbench architecture and debugging.
 	
Proficient in a variety of programming languages and standard protocols, with hands-on experience using tools like Cadence Incisive/Xcelium and Mentor Graphics ModelSim.
 	
Demonstrated ability to lead verification teams, manage projects, and drive verification activities effectively.