Digital Verification Engineer

 

 	
Languages and Tools:
 	
 -SystemVerilog
 	
 -Specman e
 	
 -Subversion, Clear Case, Perforce, Git
 	
 -Cadence IES (NCSim, ePlanner, vManager)
 	
 -Questa
 	
 -SVA/ABV

 

 	
Methodologies:
 	
-UVM for SystemVerilog
 	
-eRM
 	
-Mixed Signal Verification
 	
-Testbench Architecture & Implementation
 	
-Verification Planning

 

 	
Experience with protocols: AXI, AHB, APB, I2C, SPI.