Staff Design Verification Engineer with 10 years of experience in RISC-V-based CPU and microcontroller subsystems, leading end-to-end verification from architecture definition through signoff. Skilled at leading teams, developing scalable verification strategies, and driving execution across IP and subsystem levels.
 	
Key Highlights
 	
Architected verification infrastructures incorporating reusable UVCs, scoreboards, checkers, and reference models across multiple design hierarchies.
 	
Provided leadership to a team of verification engineers, overseeing technical execution, resource planning, and project delivery for various IP and subsystem programs.
 	
Spearheaded verification for RISC-V-based CPU and microcontroller subsystems, overseeing the complete verification lifecycle from architectural planning to signoff.
 	
Established and expanded UVM-based verification frameworks, integrating constrained-random verification, SVA, and formal methods to ensure design robustness & coverage