Digital Verification Engineer – Gate-Level Simulation (GLS)

Job Overview

Chipright is seeking an experienced Digital Verification Engineer with strong Gate-Level Simulation (GLS) experience to support the verification and validation of complex digital semiconductor designs.
The successful candidate will be responsible for executing gate-level simulations, debugging simulation failures and validating design behaviour at gate level. The role requires a strong understanding of digital verification methodologies, timing-aware simulation and the challenges associated with transitioning from RTL simulation to gate-level verification.
Candidates must have practical, hands-on experience with GLS, including post-synthesis and/or post-layout netlist simulation.

Key Responsibilities 
Execute and debug Gate-Level Simulations (GLS) using gate-level netlists.
Perform post-synthesis and post-layout simulations to verify design functionality and timing behaviour.
Run simulations with and without Standard Delay Format (SDF) back-annotation, as required.
Analyse and debug GLS failures, including timing violations, setup and hold issues, and X-propagation.
Investigate discrepancies between RTL simulation and gate-level simulation results.
Support verification of designs following synthesis, place and route, and timing optimisation.
Analyse simulation logs, waveforms and timing reports to identify and resolve issues.
Debug reset sequences, clocking behaviour, initialisation issues and race conditions encountered during gate-level simulation.
Work with digital design, physical design, STA and verification teams to identify root causes and resolve issues.
Develop, maintain and enhance simulation scripts, testbenches and regression flows.
Support sign-off activities by ensuring the design meets the required functional and timing verification criteria.
 Required Technical Experience  
Proven hands-on experience with Gate-Level Simulation (GLS) for digital IC designs.
Experience running simulations using gate-level netlists generated from synthesis and/or physical implementation.
Understanding of SDF annotation and timing-aware simulation.
Experience debugging GLS failures, including X-propagation, timing checks, setup/hold violations and RTL-to-gate discrepancies.
Strong knowledge of digital design fundamentals, synchronous logic, clocking and reset architectures.
Experience with simulation debugging using waveform viewers and log analysis.
Familiarity with Verilog and/or SystemVerilog.
Experience working with standard-cell libraries and timing models.
 Preferred Experience  
Experience with post-synthesis and post-layout GLS.
Familiarity with SDF back-annotation and timing checks.
Experience with gate-level simulation in low-power designs, including UPF-based flows.
Understanding of synthesis, static timing analysis (STA) and physical design flows.
Experience with GLS regression automation and scripting using Python, Perl, Tcl or shell scripting.
Familiarity with industry-standard EDA simulation tools, such as Synopsys VCS, Siemens Questa or Cadence Xcelium.