Experienced Digital Design Verification Engineer with years of ASIC verification experience, specialising in IP-level and top-level verification for semiconductor and mixed-signal products. Proven expertise in SystemVerilog, UVM, Specman/e, Verilog, and VHDL, with extensive experience developing verification architectures, verification plans, UVCs, scoreboards, testbenches, regression debugging, and coverage closure.
 	
Strong background in Power Management ICs (PMICs), automotive electronics, LED display systems, ambient light sensors, Wi-Fi controllers, and functional safety verification. Skilled in creating reusable verification environments, constrained-random testing, protocol verification, and top-level system validation.
 	
Protocols: SPI, I2C, UART, APB, Wishbone, IEEE 802.11, AXI
 	
Cadence and Synopsys Verification Tool Suites