Digital Verification Engineer

Digital Verification Profile
Strong hands-on experience in: SystemVerilog and UVM
Constrained random verification methodologies
Formal verification techniques
Solid understanding of digital design fundamentals (RTL design, timing, interfaces, etc.).
Proven experience in:
Testbench architecture and development
Scoreboards, monitors, and checkers
Functional and code coverage methodologies
Experience with Questa or equivalent simulation tools.
Demonstrated ability to work across digital and analog/mixed-signal interfaces.
Experience working on automotive or high-reliability semiconductor products.
Familiarity with mixed-signal verification challenges.
Exposure to AI-enabled verification flows, such as:
Coverage acceleration
Intelligent stimulus generation
Debug automation
Knowledge of modern verification flows for large subsystem or SoC-level designs.
Familiarity with scripting (Python, Tcl, or similar) for automation.