12+ years of hands-on experience architecting and executing pre-silicon verification for complex mixed-signal integrated circuits using SystemVerilog, Verilog-AMS, AMS, and DMS environments.
 	
Deep expertise in AMS, digital-centric mixed-signal, RTL, and gate-level verification for PMICs, DC-DC converters, and automotive functional-safety products.
 	
Proven ability to independently assess existing verification environments, identify methodology and coverage gaps, and implement scalable solutions.
 	
Architect advanced SystemVerilog top-level verification environments using SV-RNM, EEnet, wreal, assertions, automated checkers, and reusable verification components.
 	
Develop high-performance behavioral models for complex analog blocks, including buck converters, LDOs, ADCs, DACs, references, power stages, and modulators.
 	
Advanced proficiency with Cadence Virtuoso, ADE Assembler/Maestro, ADE Verifier, Spectre X, Xcelium, vManager, vPlanner, and JasperGold.