Senior Digital Verification Engineer with experience delivering robust UVM-based and constrained-random verification solutions for complex mixed-signal ICs.
 	
Key Highlights
 	
Led five cross-functional projects, managing planning, execution, and delivery
 	
Contributed to RISC V IP development and built an automated formal verification-based compliance workflow, enhancing compliance coverage and reducing manual validation effort
SystemVerilog, UVM, SVA, Python, Git
 	
This Engineer is recent entrant into the job market and is looking to secure a senior position preferably in Norway, Sweden, Switzerland or Scotland.