AMS Verification Engineer with experience in mixed-signal modelling and advanced CRV/CDV verification methodologies, utilizing SystemVerilog, SystemVerilog-AMS, and UVM.
 	
Key Highlights
 	
Modelling of various chip specific circuits:: ADCs, Regulators, Gate Drivers, POR circuits, Oscillators
 	
Direct and CRCDV approach to testing written in SV according to verification plan
 	
Developed automated verification workflows using Python