ASIC Verification Engineer Requirements 

We require 2–3 Specman e digital verification engineers. 

We are looking for senior engineers available in the July–December timeframe with the following skill set: 
Deep knowledge of ASIC verification methodologies (UVM, formal verification, directed testing)
Strong understanding and hands-on experience with Specman e (most important)
Solid understanding of ASIC design processes and digital design methodologies
High expertise in verifying ASICs using state-of-the-art verification and simulation tools
Knowledge of design abstraction levels (RTL, gate-level, SystemC)
Remote work (Europe)