we are currently seeking an experienced AMS Verifier for our customer.
  
Responsibilities
  
Develop and execute assigned test cases in line with the verification plan; identify and debug any issues encountered
Design, implement, and validate SystemVerilog Real Number Models (SV RNM) for analog blocks
Create test cases in UVM environments across functional, test mode, and other verification areas
Collaborate with designers and cross-functional teams throughout the verification cycle
Log, track, and drive bug resolution to closure using Jira
Document verification results for assigned blocks and actively participate in review processes
  
Qualifications
  
Bachelor’s or higher degree in Electronics Engineering or a related field
6+ years of experience in chip-level mixed-signal (AMS) verification for SoCs
Strong ability to independently analyze, troubleshoot, and debug complex issues
Hands-on experience with mixed-signal simulators and SystemVerilog/UVM-based test case development
Experience debugging SystemVerilog RNM behavioral models
Experience with GLS (Gate-Level Simulation) is a plus