DFT Engineer
    
We’re seeking an experienced Design‑for‑Test (DFT) Engineer to support our silicon development team during a critical phase of the project. You will be responsible for implementing and optimizing DFT methodologies, improving test coverage, and ensuring high‑quality test deliverables for complex SoC/ASIC designs.
  
This role is ideal for someone who thrives in fast‑paced environments, enjoys hands‑on technical problem‑solving, and can quickly integrate into an existing workflow.
    
 	
Develop, implement, and validate ATPG (Automatic Test Pattern Generation) strategies for scan, MBIST, and other test structures.
 	
 	
Analyze and improve fault coverage, identifying gaps and driving enhancements across the design.
 	
 	
Perform simulation and verification of DFT features, ensuring correctness and robustness.
 	
 	
Execute pattern retargeting and debug issues across hierarchical or multi‑die test environments.
 	
 	
Collaborate with RTL, physical design, and test engineering teams to ensure seamless integration of DFT features.
 	
 	
Generate documentation, reports, and sign‑off materials for internal and external stakeholders.
 	
 	
Support bring‑up and debug activities as needed during silicon validation.