Chipright is currently seeking an experienced analog/mixed-signal layout design engineer to support our customer's project in the development of SerDes solutions.
 
 RESPONSIBILITIES:  
Execute layout design for high‑speed, high‑performance SerDes analog and mixed‑signal circuits according to project specifications.
Perform block‑level physical implementation, including floorplanning, power distribution networks, clock and signal routing, and transistor‑level analog/mixed‑signal layout.
Contribute to post‑layout circuit performance analysis.
Support block/IP/chip‑level integration activities.
Develop realistic schedules and provide clear progress tracking and status updates.
Identify and resolve layout quality issues and offer feedback to design team
 
 EXPERIENCE:   
Strong understanding of analog and mixed‑signal layout fundamentals, including IR/EM effects, coupling and self‑capacitance, RC delay, and self‑heating.
Knowledge of high‑speed critical signal routing and shielding methodologies.
Proficiency with physical design verification tools and checks (LVS, DRC, ERC, ANT, ESD, etc.).
Experience with high‑speed SerDes block and PLL layout in advanced FinFET technologies is a plus.
Familiarity with circuit design concepts, design flows, and IC manufacturing processes..
Knowledge of digital‑on‑top or digital SoC integration flows is advantageous.
Experience with Cadence SKILL or scripting languages such as Perl, Python, or Tcl is beneficial.