DFT Engineering
 	
Built and validated DFT SoC hybrid models combining RTL and netlist representations
 	
Performed DFT design validation using IJTAG and SSN infrastructures
 	
Developed SystemVerilog UVM environments for DFT verification
 	
Validated SSH cores and EDT in INTEST and EXTEST modes
 	
Verified pattern retargeting via SSN/IJTAG scan streaming
 	
Ensured correct TDR access across multiple security levels
 	
Developed cycle-accurate TCL scripts for SSN continuity verification in highly partitioned designs with complex structures (MUXes, SSH controllers, pipelines)
 	
Delivered internal technical presentations on IJTAG network insertion using Tessent and advanced DFT debug methodologies
 	
Synthesis & Static Timing Analysis
 	
Executed RTL synthesis and static timing analysis for digital designsAnalyzed timing reports and supported timing closure activities
 	
Performed STA sign-off using industry-standard Synopsys tools
 	
Automated synthesis and STA flows using TCL and Perl scripting