Years of experience in ASIC Design Verification
 	
Strong expertise in developing verification environments using SystemVerilog and UVM methodology.
 	
Skilled in achieving IP-level functional and code coverage closure, with excellent debugging capabilities.
 	
Experienced in RTL design using Verilog HDL.
 	
HDL?s Verilog, System Verilog
 	
HDL simulator: ncverilog, VCS, Xcelium, Verdi
 	
Scripting language: Python, Perl
 	
Regression Tool: Vmanager
 	
Verification Plan: Cadence Vplanner
 	
Bug Tracking Tool: Clear-quest, Teamtrack