Experienced ASIC Verification Engineer
 	
 Programming Languages: SystemVerilog, Verilog, C++, C
 	
 Verification Methodologies: UVM
 	
 Tools: ModelSim, Xilinx ISE, Cadence Incisive, Virtuoso, Spectre, Calibre, Synopsys Verdi
 	
 Revision control systems: SVN, Perforce
 	
 Projects:

 	
 -Parity Generators Top Level Verification
 	
 -UVM RAL Top Level Generation
 	
 -GPIO Top Level Verification
 	
 -ILC Top Level Verification
 	
 -BFM I3C Verification