{"ID":20219,"post_author":"132","post_date":"2025-05-26 10:54:37","post_date_gmt":"2025-05-26 09:54:37","post_content":"

-Expertise in SoC, Subsystem, ASIC, and IP level functional verification of complex design<\/li>\r\n \t
-Expertise in UVM, System Verilog and Specman-e\/eRM language<\/li>\r\n \t
-Testbench development from scratch using the UVM-SV<\/li>\r\n \t
-Formal Verification expert using assertion language SVA and formal tools like JasperGold\/VC Formal\/OneSpin<\/li>\r\n \t
-Experience in SoC level Boot, Initialization and C-Firmware executions<\/li>\r\n \t
-Expert industry standard protocols:<\/li>\r\n \t
\u00a0-AMBA: APB, AHB\/AHB5, AXI3\/AXI4\/AXI5, ACE, AXI4-Stream, ATB<\/li>\r\n \t
\u00a0-Memory: DDRs\/LPDDRs and DFI3.0\/DFI4.0 bus protocols<\/li>\r\n \t
\u00a0-High Speed Interface: NoC (Network on Chip), Ethernet and CPRI (GSM, LTE, 4G), MIPI-DSI, PHYs etc<\/li>\r\n \t
\u00a0-Peripheral Interface: JTAG, I2C, 12S, SPI\/QSPI\/OSPI<\/li>\r\n \t
\u00a0-Others: OCP<\/li>\r\n \t
-Protocol Verification IP (VIP) or UVC development from scratch<\/li>\r\n \t
-Experience in Verilog and VHDL RTL language and understanding<\/li>\r\n \t
-Netlist Verification (Gate Level Simulation)<\/li>\r\n \t
-Low power verification methodology using UPF<\/li>\r\n<\/ul>","post_title":"E-75083","post_excerpt":"","post_status":"publish","comment_status":"open","ping_status":"open","post_password":"","post_name":"e-75083","to_ping":"","pinged":"","post_modified":"2025-05-26 10:58:54","post_modified_gmt":"2025-05-26 09:58:54","post_content_filtered":"","post_parent":0,"guid":"http:\/\/www.chipright.com\/candidate\/e-75083\/","menu_order":0,"post_type":"candidate","post_mime_type":"","comment_count":"0","filter":"raw","meta":{"desired_position":"Contract","best_fit":"ASIC Verification","experience":"17","entity_type":"Individual","on_site":"10","technologies":"5G","contact":"Alison Freer","level":"Rock Star","_edit_lock":"1748253534:132","_edit_last":"132"}}

NO

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E-75083 | Chipright Chipright

E-75083

Area of expertise: ASIC Verification

Core Technologies: 5G

Experience: 17 years

Time On Site: 10%


 	-Expertise in SoC, Subsystem, ASIC, and IP level functional verification of complex design
 	-Expertise in UVM, System Verilog and Specman-e/eRM language
 	-Testbench development from scratch using the UVM-SV
 	-Formal Verification expert using assertion language SVA and formal tools like JasperGold/VC Formal/OneSpin
 	-Experience in SoC level Boot, Initialization and C-Firmware executions
 	-Expert industry standard protocols:
 	 -AMBA: APB, AHB/AHB5, AXI3/AXI4/AXI5, ACE, AXI4-Stream, ATB
 	 -Memory: DDRs/LPDDRs and DFI3.0/DFI4.0 bus protocols
 	 -High Speed Interface: NoC (Network on Chip), Ethernet and CPRI (GSM, LTE, 4G), MIPI-DSI, PHYs etc
 	 -Peripheral Interface: JTAG, I2C, 12S, SPI/QSPI/OSPI
 	 -Others: OCP
 	-Protocol Verification IP (VIP) or UVC development from scratch
 	-Experience in Verilog and VHDL RTL language and understanding
 	-Netlist Verification (Gate Level Simulation)
 	-Low power verification methodology using UPF

Contact Us

+353 91 444 168

info@chipright.com

Unit 8B, Galway Technology Centre, Galway, Ireland

E-75083

Area of expertise: ASIC Verification

Core Technologies: 5G

Experience: 17 years

Time On Site: 10%


 	-Expertise in SoC, Subsystem, ASIC, and IP level functional verification of complex design
 	-Expertise in UVM, System Verilog and Specman-e/eRM language
 	-Testbench development from scratch using the UVM-SV
 	-Formal Verification expert using assertion language SVA and formal tools like JasperGold/VC Formal/OneSpin
 	-Experience in SoC level Boot, Initialization and C-Firmware executions
 	-Expert industry standard protocols:
 	 -AMBA: APB, AHB/AHB5, AXI3/AXI4/AXI5, ACE, AXI4-Stream, ATB
 	 -Memory: DDRs/LPDDRs and DFI3.0/DFI4.0 bus protocols
 	 -High Speed Interface: NoC (Network on Chip), Ethernet and CPRI (GSM, LTE, 4G), MIPI-DSI, PHYs etc
 	 -Peripheral Interface: JTAG, I2C, 12S, SPI/QSPI/OSPI
 	 -Others: OCP
 	-Protocol Verification IP (VIP) or UVC development from scratch
 	-Experience in Verilog and VHDL RTL language and understanding
 	-Netlist Verification (Gate Level Simulation)
 	-Low power verification methodology using UPF

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E-75083

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