Chipright have an immediate need for a Senior analog IC layout Engineer to work for our client as a layout lead. As a team lead, the chosen enginee will be expected to drive layout, define other layout engineers tasks, take layout all the way through the design flow without supervision and creating processes for continual improvement.

The chosen engineer is required to have strong experience in block-level designs, top level integration and Floorplanning , and pad ring layout of RF/high speed blocks.

A solid track record in full chip assembly and verification and Skill programming. Design kits, layout and verification tools is of interest.  

PLEASE NOTE: EU/UK working visa is critical for application 
 
Responsibilities include: 
Producing and delivering high quality layouts
Floorplanning, block level layout, top level integration and pad ring layout of RF/high speed blocks
Coordinating layouts block resources and support other team members
Conducting tape-out verification tasks which include: DRC, ANT, DUM and LVS
Preparing technical reviews and product documentation
Working with cross functional teams to deliver IC Products
 
Tools:  
Cadence Virtuoso IC6 “L,XL,GXL,” skill coding is a plus
Calibre “DRC,ANT,DUM & LVS”
Cliosoft is a plus
Layout Experience: 5-10 years
 Technology:  
180nm/ 130nm/ 65nm