MSDV Engineer
Salary: Very Attractive Rate
Location:
Contract Lead
Mixed Signal Design Verification Engineer
- Implementation of System Verilog Models for the Analog blocks
- Model vs Schematic Verification – System Verilog Test bench implementation including assertions
- Understanding of adding connect module at the interaction of schematic and model while running AMS simulations
- Understanding of UVM environment and implementing the Top Level Test cases in the environment
- Running regressions using VManager.
Contact Us
+353 91 444 168
info@chipright.com
Unit 8B, Galway Technology Centre, Galway, Ireland