Areas of Expertise
Advanced Verification Methodologies (UVM, OVM, eRM)
Architecting functional and performance verification solutions
Constraint-Random verification using SystemVerilog
Metric-Driven Verification 
RTL design and verification in VHDL and Verilog HDL
Knowledge of design flow from specification to synthesis and gate level simulation 
HDL Experience: VHDL, Verilog
Programming languages: C, C++
Scripting Languages: C shell, Perl
EDA Tool Proficiency
Questasim, VCS, Scirocco, NCsim, Xilinx, Design Compiler and SONET/SDH telecom workbench.