-Analog Layout engineer with project leader experience
- Worked on 7nm finFET technology, VREF blocks, PFDCP, Voltage regulators.
-Worked on 28nm cmos technology, battery charger, high speed driver, high speed receiver, control blocks.
-40nm and 28nm technology, working on a current source, bandgap and ADC.
-- Worked on Logic libraries, Regulator blocks, Channel clock, Summer, and CTLE block.
-Skilled in layout design tools such as Cadence Virtuoso and Alpha-SX
-Experienced in layout verification tools in Calibre and Dracula
-Broad knowledge in designing analog and mixed signal layout for both block and top
block level