Real Number Modeling/ Mixed Signal Verification Engineer:

-Developing Real Number Models for analog-mixed-signal modules: PMU, PLL, CSA, Voltage Regulator, Boost, Gate Driver or Sensing Circuits 
-Using Cadence and Synopsys tools to test functionalities and measure parameters
-Creating testing plans for System Verilog and VHDL models based on schematic simulations or requirements
-Developing Waveform Comparison tool using Python
-Using UVM to debug top level SoC tests
-Reporting model & requirement issues using JIRA
-Creating comprehensive verification reports using internal tools