Area of expertise: ASIC Verification
Core Technologies: Automotive
Experience: 20 years
Time On Site: 0%
Over 20 years of industry experience, with many successful verification projects done
Very adept at implementing new methodologies and tool flows, and sharing the knowledge with the rest of the team.
Verification methodology and EDA tools highlights:
Some formal verification using VC Formal
Advanced UVM, SystemVerilog, SVA, constrained-random functional verification
Architecture and implementation of UVM test environments from scratch
Functional coverage specification and implementation
Python verification (CocoTb)
Unit testing with SVUnit
Test Driven Development (TDD)
Matlab HDL Verifier (dpigen / codegen)
Questa, VCS, Incisive / Xcelium
Cadence vManager, Mentor Graphics Verification Run Manager
UVM Register model generation: Mentor Graphics Register Assistant
Continuous Integration (CI) with Jenkins and Gitlab
EDA tool installation and support (Xcelium, Questa)
Regression scripting, from compilation and simulation to merging and analyzing coverage results