Area of expertise: ASIC Verification
Core Technologies: Automotive
Experience: 21 years
Time On Site: 0%
A senior electrical engineer with extensive knowledge and experience in ASIC Verification and Design.
In charge of whole ASIC verification and FPGA creation/design.
Successfully completed more than 8 projects to the production stage.
Developed DVEs (Design Verification Environments) and Test Plans for Systems, ASICs and blocks levels.
Coordinated and presented DVEs / Test Plans reviews to obtain management approval.
Coached and supervised other verification engineers to accomplish their verification tasks.
Extensive knowledge and on-going usage of Verilog, C, SystemC, and SystemVerilog for verification and modeling.
Expert in Specman, OVM, VMM, UVM, and Coverage-Driven Based Functional Verification
Designed strong and efficient test strategies to verify ASICs? functionalities and measure performance.