Developing a complex mixed signal System Verilog-based test benches.
Creating a fully working UVM benches from scratch.
Maintaining and developing a set of python scripts, maintaining Jenkins automation server
and regressions.
4) Developing a base class layer used for mixed signal direct testing (WReal models).
Integrated a various set of analog stimuli functions.
Developed and integrated a Layer on top of UVM layer, adding various new functionalities
making the new environment creation faster and easier.
Created a set training courses for Verilog, System Verilog, OOP, Constraints and UVM.
Led a team of 4 verification engineers. Indicated all functionalities that need be covered.
Created and assigned tasks (using Redmine) based on the expertise of each engineer.
Supporting Lab validation of the chip.
Supporting RTL optimization and bug fixes ? RTL parametrization, code scale-ability, code
read-ability, metal-fixes