Responsible for creating and maintaining a UVM verification environment to be used on
separate module level and top level verification flows.
Responsible for the Digital module verification process (verification plan creation, test
creation and debugging, creating coverage items and checkers, creating scoreboards)
for the LIDAR digital control and SPI-to-APB bridge modules.
Responsible for creating and maintaining several UVM reusable UVCs: SPI, APB, clock
and reset generators, etc.
Responsible for running and debugging complete test regressions for
the aforementioned modules as well as for the digital top level.
Protocols used in design: SPI, APB, AXI, CSI2
Verification Methodology: UVM ? System Verilog
Tools used: Incisive Enterprise Simulator, Incisive vManager,Eclipse IDE, Gitlab, Jira