-Full Custom layout, development of parameterized cell, integration
and SoC (System on Chip), design of layout of analog, digital and mixed-signal blocks, power routing
analysis and critical connections, floorplaning, building pad-rings and encapsulations drawings, manual and
automatic routing using dedicated software;
-Large experience in check layout rules (DRC, DFM, ERC, Antenna, Stamp, ESD, Latch-up, LVS).
Preparation and documentation of tape-out delivering files, parasitic extraction and
creation of back-annotation for post-layout simulation, estimates of top blocks and sub-hierarchies,
developing scripts for automatic routing (VCAR) and SKILL scrips for automatization of layout tasks;
-Frequent use of integrated circuit design CAD tools CADENCE (Virtuoso, Composer, VCAR, First
Encounter, Assura, PVS) and MENTOR (Calibre DRC, Calibre LVS, Calibre PEX, Calibre MDPView) using advanced state-of-the art layout techniques.
-Has worked on tech nodes down to 55nm CMOS