Area of expertise: Analog Layout
Core Technologies: Telecommunications
Experience: 20 years
Time On Site: 75%
Analog/ RFIC Layout Senior Engineer
Analog blocks for power management, ADC, VLDO, TSMC 0.13um BCDMOS
Analog layout block transfer from 40nm to TSMC 22nm
Global 22nm and 28nm, TSMC 28nm, 40 nm, 45nm technologies in charge of a multifoundries process with Global, SMIC, UMC, TSMC in 40nm
interpretation and solving of LVS checks
Solving DRC, antenna and DFM checks.