Verification Engineer 

HVLs: SystemVerilog, Specman/e, SVA
HDLs: Verilog, SystemC, VHDL
Methodologies: UVM, eRM
RAL: uvm reg, vr ad
Interfacing: VPI, DPI, Specman e Reflection
Scripting Shell scripting, Python, Tcl

TOOLS
Simulators: Xcelium/Incisive (Cadence), Questasim (Siemens), VCS (Synopsys)
Planning: Cadence vManager & vPlanner, Polarion
Formal: Cadence JasperGold Formal App
IDE: DVT Eclipse, VSCode
Versioning: Git + GitLab, ClearCase, CVS
BugTracking: Jira, Mantis 
WoW: Agile/Scrum, Waterfall

SKILLS
Protocols PCIe, CPRI, AMBA AXI, APB, DDR4, Custom protocol

Projects:
L2-L3 Packet Router
DDR Memory Control
Proprietary Multi-Port Memory Controller
Packet routing switch 
AXI to Memory Bridge
Open-source verification framework - SVAUnit
CPRI Multi-Layered Bridge
High-speed Switch & Network Interface Controller