Verification engineer for digital and mixed signal designs using Cadence tools, Specman, xavcs,
eRM/OVM/UVM, IFV
- Verification for SBC(System Base Chip)) devices including: CAN, LIN, SPI, DC-DC and linear
regulators, bridges
- Behavioral model design (vhdl, verilog-a) for linear regulators, half-bridges, oscillators, chargepumps. Models are further used for verification as golden models or replacement in mixed signal
verification in slow simulations cases.
- Project technical lead for pre-silicon and post-silicon integration verification activities, including
test plan, elaboration, planning and reporting activities, reuse tests from pre-silicon to post-silicon,
requirement traceability, ISO26262 related activities.