Area of expertise: ASIC Verification
Core Technologies: Automotive
Experience: 10 years
Time On Site: 10%
Hardware description languages: Verilog, VHDL, SystemVerilog
Strong practical and academic background in the digital design, verification and
Simulation in Cadence NC-Sim, Mentor Graphics ModelSim/QuestaSim and
Aldec Riviera-Pro
Final verification of internal FPGA design using Xilinx tools
On platform debugging, Writing basic C tests for design verification
HW/SW co-verification
Functional verification using UVM. BFM or Vunit approach
Software tools:Xilinx ISE, Xilinx Vivado, Xilinx Chip Scope Pro, Xilinx EDK,
Cadence NCSim, Mentor Graphics ModelSim, QuestaSim, Altera Quartus,
Aldec Riviera-Pro
Other: C/C++,Python (basic), revisions control software(SVN, GIT).