experts at full custom physical design
Supporting your back end! Our consultants provide expert knowledge in ASIC implementation and physical verification from RTL through to GDS-II. This includes timing constraints generation, clock tree synthesis, formal verification, floorplanning, place and route, final timing closure.
Synthesis, Timing Constraints,Static Timing AnalysisSignal IntegrityPower AnalysisFormal VerificationPhysical Verification Padring DesignFull flow RTL to GDSII
Design Compiler, DFT Compiler, IC Compiler, Star RCXT, HSPICE, Primetime, Formality, Tetramax, Hercules, LVS, Dracula