What is SystemVerilog?

IEEE 1800TM SystemVerilog is the industry's first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364TM Verilog language. It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count and bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow.

What is VMM / OVM?

The Verification Methodology Manual (VMM) is a set of guidelines and recommendations to be followed when building an advanced verification environment. It is pioneered within the semiconductor industry by Synopsys. VMM is open source and Synopsys have donated the entire library to the Accellera committee to enable interoperability standardization across EDA tools.
The Open Verification Methodology (OVM) is a set of guidelines and recommendations to be followed when building an advanced verification environment. It is pioneered within the semi-conductor industry by Mentor Graphics and Cadence. OVM is open source and has been donated to the Accellera committee to enable interoperability standardization across EDA tools

If you are new to SystemVerilog and VMM / OVM, the best way to view them is as follows: “VMM / OVM are a set of object orientated classes and macros built from using the SystemVerilog language that empowers verification engineers to build standard verification solutions”.

Chipright's VMM and OVM Solutions

Whilst VMM / OVM and SystemVerilog together provide the stepping stones you need to work with when building an advanced verification environment, they don’t actually specify how you need to strategically design your verification environment to leverage the maximum benefit from this new technology. To do this you need to analyze your verification requirements up front, decide on the components you will need and figure out how to get them working together without running into a steep learning curve on a live project.

Chipright is aware of the benefits and pitfalls that differing verification methodologies can provide. Having implemented several successful verification projects to date we are capable of providing assistance to new and existing customers to migrate their existing verification infrastructure and leverage the best of what the next generation methodologies have on offer.   

Our customer base can leverage our VIP components and create their own components and test benches with the Pluto product.

If you would like to find out some more about constrained random verification methods, please take a look at a paper we published at ISSC 2008 here.